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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">MVFR0_EL1, AArch32 Media and VFP Feature Register 0</h1><p>The MVFR0_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.</p>

      
        <p>Must be interpreted with <a href="AArch64-mvfr1_el1.html">MVFR1_EL1</a> and <a href="AArch64-mvfr2_el1.html">MVFR2_EL1</a>.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch64 System register MVFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-mvfr0.html">MVFR0[31:0]</a>.</p>
        <p>In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.</p>
      <h2>Attributes</h2>
        <p>MVFR0_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><h3>When AArch32 is supported:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">FPRound</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">FPShVec</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">FPSqrt</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">FPDivide</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">FPTrap</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">FPDP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">FPSP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">SIMDReg</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_28">FPRound, bits [31:28]</h4><div class="field">
      <p>Floating-Point Rounding modes. Indicates whether the floating-point implementation provides support for rounding modes. Defined values are:</p>
    <table class="valuetable"><tr><th>FPRound</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not implemented, or only Round to Nearest mode supported, except that Round towards Zero mode is supported for VCVT instructions that always use that rounding mode regardless of the <a href="AArch32-fpscr.html">FPSCR</a> setting.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>All rounding modes supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-27_24">FPShVec, bits [27:24]</h4><div class="field">
      <p>Short Vectors. Indicates whether the floating-point implementation provides support for the use of short vectors. Defined values are:</p>
    <table class="valuetable"><tr><th>FPShVec</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Short vectors not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Short vector operation supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-23_20">FPSqrt, bits [23:20]</h4><div class="field">
      <p>Square Root. Indicates whether the floating-point implementation provides support for the ARMv6 VFP square root operations. Defined values are:</p>
    <table class="valuetable"><tr><th>FPSqrt</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported in hardware.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>The VSQRT.F32 instruction also requires the single-precision floating-point attribute, bits [7:4], and the VSQRT.F64 instruction also requires the double-precision floating-point attribute, bits [11:8].</p></div><h4 id="fieldset_0-19_16">FPDivide, bits [19:16]</h4><div class="field">
      <p>Indicates whether the floating-point implementation provides support for VFP divide operations. Defined values are:</p>
    <table class="valuetable"><tr><th>FPDivide</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported in hardware.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>The VDIV.F32 instruction also requires the single-precision floating-point attribute, bits [7:4], and the VDIV.F64 instruction also requires the double-precision floating-point attribute, bits [11:8].</p></div><h4 id="fieldset_0-15_12">FPTrap, bits [15:12]</h4><div class="field">
      <p>Floating Point Exception Trapping. Indicates whether the floating-point implementation provides support for exception trapping. Defined values are:</p>
    <table class="valuetable"><tr><th>FPTrap</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>A value of <span class="binarynumber">0b0001</span> indicates that, when the corresponding trap is enabled, a floating-point exception generates an exception.</p></div><h4 id="fieldset_0-11_8">FPDP, bits [11:8]</h4><div class="field">
      <p>Double Precision. Indicates whether the floating-point implementation provides support for double-precision operations. Defined values are:</p>
    <table class="valuetable"><tr><th>FPDP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported in hardware.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supported, VFPv2.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Supported, VFPv3, VFPv4, or Armv8. VFPv3 and Armv8 add an instruction to load a double-precision floating-point constant, and conversions between double-precision and fixed-point values.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0010</span>.</p>
<p>A value of <span class="binarynumber">0b0001</span> or <span class="binarynumber">0b0010</span> indicates support for all VFP double-precision instructions in the supported version of VFP, except that, in addition to this field being nonzero:</p>
<ul>
<li>VSQRT.F64 is only available if the Square root field is <span class="binarynumber">0b0001</span>.
</li><li>VDIV.F64 is only available if the Divide field is <span class="binarynumber">0b0001</span>.
</li><li>Conversion between double-precision and single-precision is only available if the single-precision field is nonzero.
</li></ul></div><h4 id="fieldset_0-7_4">FPSP, bits [7:4]</h4><div class="field">
      <p>Single Precision. Indicates whether the floating-point implementation provides support for single-precision operations. Defined values are:</p>
    <table class="valuetable"><tr><th>FPSP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported in hardware.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supported, VFPv2.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Supported, VFPv3 or VFPv4. VFPv3 adds an instruction to load a single-precision floating-point constant, and conversions between single-precision and fixed-point values.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0010</span>.</p>
<p>A value of <span class="binarynumber">0b0001</span> or <span class="binarynumber">0b0010</span> indicates support for all VFP single-precision instructions in the supported version of VFP, except that, in addition to this field being nonzero:</p>
<ul>
<li>VSQRT.F32 is only available if the Square root field is <span class="binarynumber">0b0001</span>.
</li><li>VDIV.F32 is only available if the Divide field is <span class="binarynumber">0b0001</span>.
</li><li>Conversion between double-precision and single-precision is only available if the double-precision field is nonzero.
</li></ul></div><h4 id="fieldset_0-3_0">SIMDReg, bits [3:0]</h4><div class="field">
      <p>Advanced SIMD registers. Indicates whether the Advanced SIMD and floating-point implementation provides support for the Advanced SIMD and floating-point register bank. Defined values are:</p>
    <table class="valuetable"><tr><th>SIMDReg</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The implementation has no Advanced SIMD and floating-point support.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>The implementation includes floating-point support with 16 x 64-bit registers.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>The implementation includes Advanced SIMD and floating-point support with 32 x 64-bit registers.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0010</span>.</p></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">UNKNOWN</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_1-63_0">UNKNOWN</a></td></tr></tbody></table><h4 id="fieldset_1-63_0">Bits [63:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing MVFR0_EL1</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, MVFR0_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0000</td><td>0b0011</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        X[t, 64] = MVFR0_EL1;
elsif PSTATE.EL == EL2 then
    X[t, 64] = MVFR0_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = MVFR0_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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